When switching wide-band information flows transmitted on a 2.048 Mbit/s PCM group, one of the technical problems to cope with is that of keeping the sequencing of the individual channels of a frame while passing through a time switching stage. In particular, a certain channel sequence of a frame at the switching stage input is required to be maintained equal in the outgoing frame too. Which is obtained today only for the bits of each channel, as far as 64 kbit/s PCM channel switching is concerned.
On the contrary it would be useful to obtain also a sequencing of the individual channels, in order to ensure the correct switching of signals occupying more than one channel e.g. signals derived from video-signal coding equipment.
In said case it is compulsory to maintain the correct time succession of all the individual channels forming the outgoing information flow, to correctly recover the TV image received.
Nowadays logic circuits capable of recognizing the individual frame numbers and, inside the frames, the individual channel numbers are already known. Said circuits are elements necessary to a frame synchronizer, as they supply the initial data for the maintenance of the flow sequencing.
However, said circuits cannot intervene to carry out the required synchronisation.